1. Field of the Invention
The present invention relates to a image sensor and a method for fabricating the same. Although the present invention is suitable for a wide scope of applications, it is particularly suitable for enhancing image sensor characteristics.
2. Discussion of the Related Art
An image sensor is a semiconductor device that converts an optical image into an electrical signal. A complementary MOS (CMOS) image sensor includes a photosensing device, such as a photodiode, and a CMOS logic circuit made up of a plurality of MOS transistors corresponding to the number of pixels fabricated with CMOS technology. A three-transistor (3T) CMOS image sensor includes one photodiode and three transistors, and a four-transistor (4T) CMOS image sensor includes one photodiode and four transistors.
Referring to FIG. 1, a unit pixel of a general 3T-type CMOS image sensor includes one photodiode PD and three NMOS transistors Rx, Dx, and Sx. The cathode of the photodiode PD is connected to the drain of the first NMOS transistor Rx and the gate of the second NMOS transistor Dx. The sources of the first and second NMOS transistors Rx and Dx are connected to a power line supplying a reference voltage VR, and a gate of the first NMOS transistor Rx is connected to a reset line supplying a reset signal. The source of the third NMOS transistor Sx is connected to the drain of the second NMOS transistor Dx. The drain of the third NMOS transistor Sx is connected to a read circuit (not shown). The gate of the third NMOS transistor Sx is connected to a row select line supplying a select signal.
Referring to FIG. 2, an active region 10 is defined in a unit pixel of the general 3T-type CMOS image sensor. A photodiode 20 is formed on a wide portion of the active region 10, and other parts of the active region are overlapped by three gate electrodes 120, 130, and 140 to configure a reset transistor Dx, a drive transistor Dx, and a select transistor Sx, respectively. The exposed portions of the active region 10 of each transistor is doped with impurity ions to become corresponding source/drain regions. A power voltage Vdd is applied to the source/drain regions between the reset and drive transistors Rx and Dx. A plurality of signal lines (not shown) are respectively connected to the gate electrodes and connect the source/drain region of the select transistor Sx to a read circuit (not shown). A pad is provided to each of the signal lines to connect to an external drive circuit.
FIGS. 3A-3F illustrate a method of fabricating a CMOS image sensor having a vertical photodiode structure according to the related art.
Referring to FIG. 3A, a pixel array 32, configured with a plurality of photodiodes for respectively sensing R, G, and B signals is formed in a photodiode area by selectively implanting impurity ions in a semiconductor substrate 31, thereby imparting a different depth to each of the three types of photodiode. A device (not shown) for signal processing is formed on the semiconductor substrate 310, including the pixel array 32. Multi-layer metal lines (not shown) are formed to connect the respective elements. An insulating interlayer 33 is formed over the semiconductor substrate 31. A protective layer 34 is formed to protect a device against moisture and impacts by forming an oxide layer on the insulating interlayer 33.
Referring to FIG. 3B, the protective layer 34 is coated with a photoresist, which is selectively patterned by exposure and development steps to form a photoresist pattern 35 exposing a portion of the protective layer 34 that overlaps the pixel array 32.
Referring to FIG. 3C, the exposed portion of the protective layer 34 is selectively removed using the photoresist pattern 35 as a mask, to form a pad opening that exposes a metal pad formed in a pad area of the semiconductor substrate 31.
Referring to FIG. 3D, the photoresist pattern 35 is removed. Then, photolithography is selectively carried out on the insulating interlayer 33 on the pixel array 32, including a dry etching process, to form a trench 36 having a predetermined depth in the insulating interlayer 33 on the pixel array 32.
Referring to FIG. 3E, the semiconductor substrate 31 and the trench 36 are coated with a microlens photoresist layer 37a. 
Referring to FIG. 3F, the microlens photoresist layer 37a is selectively patterned. A reflowing process is carried out on the patterned photoresist layer to form a plurality of microlenses 37 on the insulating interlayer 33 to be spaced apart from one another within the trench 36.
The formation of the trench 36 effectively reduces the distance between the pixel array 32 and microlenses to be formed later so that enhanced photosensitivity may be obtained. In the trench, however, the vertical profiles of the insulating interlayer 33 and the protective layer 34, existing at the inner sidewalls of the trench 36, prevent the photoresist layer 37a from having a uniform thickness. That is, the thickness uniformity is degraded by a striation occurring while coating the trench with the microlens photoresist layer. The striation is impressed upon the under side of the photoresist layer 37a due to the sharp upper edge of the inner sidewalls of the trench 36 and is generated along the entire length of the trench, thereby thinning the photoresist layer at two sites that appear as stripes on either side of the trench.